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小紅帽技術論壇 : Powered by vBulletin version 2.2.9 小紅帽技術論壇 > 電腦類 > 程式設計討論區 > VHDL如何做小數運算《問題》
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alanasakura
新進會員


註冊日期: Dec 2010
來自:
發表文章數: 1

VHDL如何做小數運算《問題》

這是老師教的VHDL-FFT 寫得差不多了 可是後面遇到個問題
column0 <= '0';
column1 <= '1';
twiddle_zero <=0.0;
..
..
..

twiddle_Im13 <= 0.4339;
twiddle_Im14 <= 0.4067;
twiddle_Im15 <= 0.3827;
就是這20幾行的程式 我必須輸入小數點 可是我把他宣告成real 但是使中沒辦法過編譯 爬文告訴我說可以用除法(例-0.5=-1/2)或是向量(例:1101 0110)輸入 但是我始終不知該如何使用 希望有高手可以幫幫忙


以下是我的程式 紅色地方式虛要大大們幫忙的 不知如何改@@!


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
package fft_defs2 is
constant INT_SIZE : integer := 16;
constant INTRANGE : integer := 64;
constant intr : integer := 63;
constant intr3 :integer :=3;
type integer_vector is array (0 to 15) of integer
range -INTRANGE to INTRANGE;
constant FIX_FACT : integer := 16;



--signal twiddle_Re0,twiddle_Re1,twiddle_Re2,twiddle_Re3,twiddle_Re4,
-- twiddle_Re5,twiddle_Re6, twiddle_Re7,twiddle_Re8,twiddle_Re9,twiddle_Re10,
-- twiddle_Re11,twiddle_Re12,twiddle_Re13, twiddle_Re14,twiddle_Re15,
-- iddle_Im1,iddle_Im2,iddle_Im3,iddle_Im4,iddle_Im5,iddle_Im6,iddle_Im7,
-- iddle_Im8,iddle_Im9,iddle_Im10,iddle_Im11,iddle_Im12,iddle_Im13,iddle_Im14,
-- iddle_Im15 :real;

end fft_defs2;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;
library work;
use work.fft_defs2.all;
entity fft_ok is
port ( x_in_Re0 : in integer range -INTRANGE to INTRANGE;
x_in_Re1 : in integer range -INTRANGE to INTRANGE;
x_in_Re2 : in integer range -INTRANGE to INTRANGE;
x_in_Re3 : in integer range -INTRANGE to INTRANGE;
x_in_Re4 : in integer range -INTRANGE to INTRANGE;
x_in_Re5 : in integer range -INTRANGE to INTRANGE;
x_in_Re6 : in integer range -INTRANGE to INTRANGE;
x_in_Re7 : in integer range -INTRANGE to INTRANGE;
x_in_Re8 : in integer range -INTRANGE to INTRANGE;
x_in_Re9 : in integer range -INTRANGE to INTRANGE;
x_in_R10 : in integer range -INTRANGE to INTRANGE;
x_in_R11 : in integer range -INTRANGE to INTRANGE;
x_in_R12 : in integer range -INTRANGE to INTRANGE;
x_in_R13 : in integer range -INTRANGE to INTRANGE;
x_in_R14 : in integer range -INTRANGE to INTRANGE;
x_in_R15 : in integer range -INTRANGE to INTRANGE;
x_in_Im0 : in integer range -INTRANGE to INTRANGE;
x_in_Im1 : in integer range -INTRANGE to INTRANGE;
x_in_Im2 : in integer range -INTRANGE to INTRANGE;
x_in_Im3 : in integer range -INTRANGE to INTRANGE;
x_in_Im4 : in integer range -INTRANGE to INTRANGE;
x_in_Im5 : in integer range -INTRANGE to INTRANGE;
x_in_Im6 : in integer range -INTRANGE to INTRANGE;
x_in_Im7 : in integer range -INTRANGE to INTRANGE;
x_in_Im8 : in integer range -INTRANGE to INTRANGE;
x_in_Im9 : in integer range -INTRANGE to INTRANGE;
x_in_I10 : in integer range -INTRANGE to INTRANGE;
x_in_I11 : in integer range -INTRANGE to INTRANGE;
x_in_I12 : in integer range -INTRANGE to INTRANGE;
x_in_I13 : in integer range -INTRANGE to INTRANGE;
x_in_I14 : in integer range -INTRANGE to INTRANGE;
x_in_I15 : in integer range -INTRANGE to INTRANGE;

out_R0 : out integer range -INTRANGE to INTRANGE;
out_R1 : out integer range -INTRANGE to INTRANGE;
out_R2 : out integer range -INTRANGE to INTRANGE;
out_R3 : out integer range -INTRANGE to INTRANGE;
out_R4 : out integer range -INTRANGE to INTRANGE;
out_R5 : out integer range -INTRANGE to INTRANGE;
out_R6 : out integer range -INTRANGE to INTRANGE;
out_R7 : out integer range -INTRANGE to INTRANGE;
out_R8 : out integer range -INTRANGE to INTRANGE;
out_R9 : out integer range -INTRANGE to INTRANGE;
outR10 : out integer range -INTRANGE to INTRANGE;
outR11 : out integer range -INTRANGE to INTRANGE;
outR12 : out integer range -INTRANGE to INTRANGE;
outR13 : out integer range -INTRANGE to INTRANGE;
outR14 : out integer range -INTRANGE to INTRANGE;
outR15 : out integer range -INTRANGE to INTRANGE;
out_I0 : out integer range -INTRANGE to INTRANGE;
out_I1 : out integer range -INTRANGE to INTRANGE;
out_I2 : out integer range -INTRANGE to INTRANGE;
out_I3 : out integer range -INTRANGE to INTRANGE;
out_I4 : out integer range -INTRANGE to INTRANGE;
out_I5 : out integer range -INTRANGE to INTRANGE;
out_I6 : out integer range -INTRANGE to INTRANGE;
out_I7 : out integer range -INTRANGE to INTRANGE;
out_I8 : out integer range -INTRANGE to INTRANGE;
out_I9 : out integer range -INTRANGE to INTRANGE;
outI10 : out integer range -INTRANGE to INTRANGE;
outI11 : out integer range -INTRANGE to INTRANGE;
outI12 : out integer range -INTRANGE to INTRANGE;
outI13 : out integer range -INTRANGE to INTRANGE;
outI14 : out integer range -INTRANGE to INTRANGE;
outI15 : out integer range -INTRANGE to INTRANGE;
clk : in std_logic;
reset : in std_logic );
end fft_ok;
architecture structural of fft_ok is
component radix_new0
port (
x_Re : in integer range -INTRANGE to INTRANGE;
xN4_Re : in integer range -INTRANGE to INTRANGE;
xN2_Re : in integer range -INTRANGE to INTRANGE;
x3N4_Re : in integer range -INTRANGE to INTRANGE;
x_Im : in integer range -INTRANGE to INTRANGE;
xN4_Im : in integer range -INTRANGE to INTRANGE;
xN2_Im : in integer range -INTRANGE to INTRANGE;
x3N4_Im : in integer range -INTRANGE to INTRANGE;

y_Re : out real ;--integer range -INTRANGE to INTRANGE;
g_Re : out real ;--integer range -INTRANGE to INTRANGE;
z_Re : out real ;--integer range -INTRANGE to INTRANGE;
h_Re : out real ;--integer range -INTRANGE to INTRANGE;
y_Im : out real ;--integer range -INTRANGE to INTRANGE;
g_Im : out real ;--integer range -INTRANGE to INTRANGE;
z_Im : out real ;--integer range -INTRANGE to INTRANGE;
h_Im : out real ;--integer range -INTRANGE to INTRANGE;
clk : in std_logic;
reset : in std_logic;
column : in std_logic;
W_l_Re : in real ;--integer range -INTRANGE to INTRANGE;
W_l_Im : in real ;--integer range -INTRANGE to INTRANGE;
W_2l_Re : in real ;--integer range -INTRANGE to INTRANGE;
W_2l_Im : in real ;--integer range -INTRANGE to INTRANGE;
W_3l_Re : in real ;--integer range -INTRANGE to INTRANGE;
W_3l_Im : in real );--integer range -INTRANGE to INTRANGE
end component;
component radix_new1
port (
x_Re : in real ;--integer range -INTRANGE to INTRANGE;
xN4_Re : in real ;--integer range -INTRANGE to INTRANGE;
xN2_Re : in real ;--integer range -INTRANGE to INTRANGE;
x3N4_Re : in real ;--integer range -INTRANGE to INTRANGE;
x_Im : in real ;--integer range -INTRANGE to INTRANGE;
xN4_Im : in real ;--integer range -INTRANGE to INTRANGE;
xN2_Im : in real ;--integer range -INTRANGE to INTRANGE;
x3N4_Im : in real ;--integer range -INTRANGE to INTRANGE;

y_Re : out real ;--integer range -INTRANGE to INTRANGE;
g_Re : out real ;--integer range -INTRANGE to INTRANGE;
z_Re : out real ;--integer range -INTRANGE to INTRANGE;
h_Re : out real ;--integer range -INTRANGE to INTRANGE;
y_Im : out real ;--integer range -INTRANGE to INTRANGE;
g_Im : out real ;--integer range -INTRANGE to INTRANGE;
z_Im : out real ;--integer range -INTRANGE to INTRANGE;
h_Im : out real ;--integer range -INTRANGE to INTRANGE;
clk : in std_logic;
reset : in std_logic;
column : in std_logic;
W_l_Re : in real ;--integer range -INTRANGE to INTRANGE;
W_l_Im : in real ;--integer range -INTRANGE to INTRANGE;
W_2l_Re : in real ;--integer range -INTRANGE to INTRANGE;
W_2l_Im : in real ;--integer range -INTRANGE to INTRANGE;
W_3l_Re : in real ;--integer range -INTRANGE to INTRANGE;
W_3l_Im : in real );-- integer range -INTRANGE to INTRANGE
end component;
signal twiddle_Re0 : real ;--range --INTRANGE to INTRANGE;
signal twiddle_Re1 : real ;--rangerange --INTRANGE to INTRANGE;
signal twiddle_Re2 : real ;--rangerange --INTRANGE to INTRANGE;
signal twiddle_Re3 : real ;--rangerange --INTRANGE to INTRANGE;
signal twiddle_Re4 : real ;--rangerange --INTRANGE to INTRANGE;
signal twiddle_Re5 : real ;--rangerange --INTRANGE to INTRANGE;
signal twiddle_Re6 : real ;--rangerange --INTRANGE to INTRANGE;
signal twiddle_Re7 : real ;--rangerange --INTRANGE to INTRANGE;
signal twiddle_Re8 : real ;--rangerange --INTRANGE to INTRANGE;
signal twiddle_Re9 : real ;--rangerange --INTRANGE to INTRANGE;
signal twiddle_Re10 : real ;--rangerange--INTRANGE to INTRANGE;
signal twiddle_Re11 : real ;--rangerange -INTRANGE to INTRANGE;
signal twiddle_Re12 : real ;--rangerange -INTRANGE to INTRANGE;
signal twiddle_Re13 : real ;--rangerange -INTRANGE to INTRANGE;
signal twiddle_Re14 : real ;--rangerange -INTRANGE to INTRANGE;
signal twiddle_Re15 : real ;--rangerange -INTRANGE to INTRANGE;

signal twiddle_Im0 : real ;--rangerange -INTRANGE to INTRANGE;
signal twiddle_Im1 : real ;--rangerange -INTRANGE to INTRANGE;
signal twiddle_Im2 : real ;--rangerange -INTRANGE to INTRANGE;
signal twiddle_Im3 : real ;--rangerange -INTRANGE to INTRANGE;
signal twiddle_Im4 : real ;--rangerange -INTRANGE to INTRANGE;
signal twiddle_Im5 : real ;--rangerange -INTRANGE to INTRANGE;
signal twiddle_Im6 : real ;--rangerange -INTRANGE to INTRANGE;
signal twiddle_Im7 : real ;--rangerange -INTRANGE to INTRANGE;
signal twiddle_Im8 : real ;--rangerange -INTRANGE to INTRANGE;
signal twiddle_Im9 : real ;--rangerange -INTRANGE to INTRANGE;
signal twiddle_Im10 : real ;--rangerange -INTRANGE to INTRANGE;
signal twiddle_Im11 : real ;--rangerange -INTRANGE to INTRANGE;
signal twiddle_Im12 : real ;--rangerange -INTRANGE to INTRANGE;
signal twiddle_Im13 : real ;--rangerange -INTRANGE to INTRANGE;
signal twiddle_Im14 : real ;--rangerange -INTRANGE to INTRANGE;
signal twiddle_Im15 : real ;--rangerange -INTRANGE to INTRANGE;
signal twiddle_zero : real ;--rangerange -INTRANGE to INTRANGE;
signal x_out_Re0 : integer range -INTRANGE to INTRANGE;
signal x_out_Re1 : integer range -INTRANGE to INTRANGE;
signal x_out_Re2 : integer range -INTRANGE to INTRANGE;
signal x_out_Re3 : integer range -INTRANGE to INTRANGE;
signal x_out_Re4 : integer range -INTRANGE to INTRANGE;
signal x_out_Re5 : integer range -INTRANGE to INTRANGE;
signal x_out_Re6 : integer range -INTRANGE to INTRANGE;
signal x_out_Re7 : integer range -INTRANGE to INTRANGE;
signal x_out_Re8 : integer range -INTRANGE to INTRANGE;
signal x_out_Re9 : integer range -INTRANGE to INTRANGE;
signal x_out_Re10 : integer range -INTRANGE to INTRANGE;
signal x_out_Re11 : integer range -INTRANGE to INTRANGE;
signal x_out_Re12 : integer range -INTRANGE to INTRANGE;
signal x_out_Re13 : integer range -INTRANGE to INTRANGE;
signal x_out_Re14 : integer range -INTRANGE to INTRANGE;
signal x_out_Re15 : integer range -INTRANGE to INTRANGE;
signal x_out_Im0 : integer range -INTRANGE to INTRANGE;
signal x_out_Im1 : integer range -INTRANGE to INTRANGE;
signal x_out_Im2 : integer range -INTRANGE to INTRANGE;
signal x_out_Im3 : integer range -INTRANGE to INTRANGE;
signal x_out_Im4 : integer range -INTRANGE to INTRANGE;
signal x_out_Im5 : integer range -INTRANGE to INTRANGE;
signal x_out_Im6 : integer range -INTRANGE to INTRANGE;
signal x_out_Im7 : integer range -INTRANGE to INTRANGE;
signal x_out_Im8 : integer range -INTRANGE to INTRANGE;
signal x_out_Im9 : integer range -INTRANGE to INTRANGE;
signal x_out_Im10 : integer range -INTRANGE to INTRANGE;
signal x_out_Im11 : integer range -INTRANGE to INTRANGE;
signal x_out_Im12 : integer range -INTRANGE to INTRANGE;
signal x_out_Im13 : integer range -INTRANGE to INTRANGE;
signal x_out_Im14 : integer range -INTRANGE to INTRANGE;
signal x_out_Im15 : integer range -INTRANGE to INTRANGE;
signal sig_vector_Re0 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Re1 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Re2 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Re3 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Re4 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Re5 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Re6 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Re7 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Re8 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Re9 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Re10 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Re11 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Re12 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Re13 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Re14 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Re15 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Im0 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Im1 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Im2 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Im3 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Im4 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Im5 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Im6 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Im7 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Im8 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Im9 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Im10 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Im11 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Im12 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Im13 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Im14 : real ;--integer range -INTRANGE to INTRANGE;
signal sig_vector_Im15 : real ;--integer range -INTRANGE to INTRANGE;
signal column0:std_logic;
signal column1:std_logic;
begin -- behavioral


column0 <= '0';
column1 <= '1';
twiddle_zero <=0.0;

twiddle_Re0 <= 1.0;
twiddle_Re1 <= -1.0;
twiddle_Re2 <= -0.5;
twiddle_Re3 <= 0.0;
twiddle_Re4 <= 0.309;
twiddle_Re5 <= 0.5;
twiddle_Re6 <= 0.6235;
twiddle_Re7 <= 0.7071;
twiddle_Re8 <= 0.7660;
twiddle_Re9 <= 0.8090;
twiddle_Re10 <= 0.8413;
twiddle_Re11 <= 0.866;
twiddle_Re12 <= 0.8855;
twiddle_Re13 <= 0.9010;
twiddle_Re14 <= 0.9135;
twiddle_Re15 <= 0.9239;

twiddle_Im0 <= 0.0;
twiddle_Im1 <= 0.0;
twiddle_Im2 <= 0.866;
twiddle_Im3 <= 1.0;
twiddle_Im4 <= 0.9511;
twiddle_Im5 <= 0.866;
twiddle_Im6 <= 0.7818;
twiddle_Im7 <= 0.7071;
twiddle_Im8 <= 0.6428;
twiddle_Im9 <= 0.5878;
twiddle_Im10 <= 0.5406;
twiddle_Im11 <= 0.5;
twiddle_Im12 <= 0.4647;
twiddle_Im13 <= 0.4339;
twiddle_Im14 <= 0.4067;
twiddle_Im15 <= 0.3827;


--00
radix0 : radix_new0

port map( x_Re => x_in_Re0, xN4_Re => x_in_Re4,
xN2_Re => x_in_Re8, x3N4_Re=> x_in_R12,
x_Im => x_in_Im0, xN4_Im => x_in_Im4,
xN2_Im => x_in_Im8, x3N4_Im => x_in_I12,

y_Re => sig_vector_Re0, g_Re => sig_vector_Re8,
z_Re => sig_vector_Re4, h_Re => sig_vector_Re12,
y_Im => sig_vector_Im0, g_Im => sig_vector_Im8,
z_Im => sig_vector_Im4,h_Im => sig_vector_Im12,
clk => clk, reset => reset ,column => column0,
W_l_Re => twiddle_Re0, W_l_Im => twiddle_Im0,
W_2l_Re => twiddle_Re0, W_2l_Im => twiddle_Im0,
W_3l_Re => twiddle_Re0, W_3l_Im => twiddle_Im0);

--01
radix1 : radix_new0

port map ( x_Re => x_in_Re1, xN4_Re => x_in_Re5,
xN2_Re => x_in_Re9, x3N4_Re=> x_in_R13,
x_Im => x_in_Im1, xN4_Im => x_in_Im5,
xN2_Im => x_in_Im9, x3N4_Im => x_in_I13,

y_Re => sig_vector_Re1, g_Re => sig_vector_Re9,
z_Re => sig_vector_Re5, h_Re => sig_vector_Re13,
y_Im => sig_vector_Im1, g_Im => sig_vector_Im9,
z_Im => sig_vector_Im5,h_Im => sig_vector_Im13,
clk => clk, reset => reset , column =>column0,
W_l_Re => twiddle_Re1, W_l_Im => twiddle_Im1,
W_2l_Re => twiddle_Re2, W_2l_Im => twiddle_Im2,
W_3l_Re => twiddle_Re3, W_3l_Im => twiddle_Im3);
--02
radix2 : radix_new0
port map ( x_Re => x_in_Re2, xN4_Re => x_in_Re6,
xN2_Re => x_in_R10, x3N4_Re=> x_in_R14,
x_Im => x_in_Im2, xN4_Im => x_in_Im6,
xN2_Im => x_in_I10, x3N4_Im => x_in_I14,
y_Re => sig_vector_Re2, g_Re => sig_vector_Re10,
z_Re => sig_vector_Re6, h_Re => sig_vector_Re14,
y_Im => sig_vector_Im2, g_Im => sig_vector_Im10,
z_Im => sig_vector_Im6,h_Im => sig_vector_Im14,
clk => clk, reset => reset , column =>column0,
W_l_Re => twiddle_Re2, W_l_Im => twiddle_Im2,
W_2l_Re => twiddle_Re4, W_2l_Im => twiddle_Im4,
W_3l_Re => twiddle_Re6, W_3l_Im => twiddle_Im6);
--03
radix3 : radix_new0
port map ( x_Re => x_in_Re3, xN4_Re => x_in_Re7,
xN2_Re => x_in_R11, x3N4_Re=> x_in_R15,
x_Im => x_in_Im3, xN4_Im => x_in_Im7,
xN2_Im => x_in_I11, x3N4_Im => x_in_I15,
y_Re => sig_vector_Re3, g_Re => sig_vector_Re11,
z_Re => sig_vector_Re7, h_Re => sig_vector_Re15,
y_Im => sig_vector_Im3, g_Im => sig_vector_Im11,
z_Im => sig_vector_Im7,h_Im => sig_vector_Im15,
clk => clk, reset => reset , column =>column0,
W_l_Re => twiddle_Re3, W_l_Im => twiddle_Im3,
W_2l_Re => twiddle_Re6, W_2l_Im => twiddle_Im6,
W_3l_Re => twiddle_Re9, W_3l_Im => twiddle_Im9 );
radix10 : radix_new1
port map ( x_Re =>sig_vector_Re0, xN4_Re => sig_vector_Re1,
xN2_Re => sig_vector_Re2, x3N4_Re=> sig_vector_Re3,
x_Im => sig_vector_Im0, xN4_Im =>sig_vector_Im1,
xN2_Im => sig_vector_Im2, x3N4_Im => sig_vector_Im3,
y_Re => X_out_Re0, g_Re => X_out_Re8,
z_Re => X_out_Re4, h_Re => X_out_Re12,
y_Im => X_out_Im0, g_Im => X_out_Im8,
z_Im => X_out_Im4, h_Im => X_out_Im12,
clk => clk,reset => reset, column => column1,
W_l_Re => twiddle_zero , W_l_Im =>twiddle_zero ,
W_2l_Re => twiddle_zero, W_2l_Im => twiddle_zero,
W_3l_Re => twiddle_zero, W_3l_Im => twiddle_zero );
radix11 : radix_new1
port map ( x_Re =>sig_vector_Re4, xN4_Re => sig_vector_Re5,
xN2_Re => sig_vector_Re6, x3N4_Re=> sig_vector_Re7,
x_Im => sig_vector_Im4, xN4_Im =>sig_vector_Im5,
xN2_Im => sig_vector_Im6, x3N4_Im => sig_vector_Im7,
y_Re => X_out_Re1, g_Re => X_out_Re9,
z_Re => X_out_Re5, h_Re => X_out_Re13,
y_Im => X_out_Im1, g_Im => X_out_Im9,
z_Im => X_out_Im5, h_Im => X_out_Im13,
clk => clk,reset => reset, column => column1 ,
W_l_Re => twiddle_zero , W_l_Im =>twiddle_zero ,
W_2l_Re => twiddle_zero, W_2l_Im => twiddle_zero,
W_3l_Re => twiddle_zero, W_3l_Im => twiddle_zero);
radix12 : radix_new1
port map ( x_Re =>sig_vector_Re8, xN4_Re => sig_vector_Re9,
xN2_Re => sig_vector_Re10, x3N4_Re=> sig_vector_Re11,
x_Im => sig_vector_Im8, xN4_Im =>sig_vector_Im9,
xN2_Im => sig_vector_Im10, x3N4_Im => sig_vector_Im11,
y_Re => X_out_Re2, g_Re => X_out_Re10,
z_Re => X_out_Re6, h_Re => X_out_Re14,
y_Im => X_out_Im2, g_Im => X_out_Im10,
z_Im => X_out_Im6, h_Im => X_out_Im14,
clk => clk,reset => reset, column => column1,
W_l_Re => twiddle_zero , W_l_Im =>twiddle_zero ,
W_2l_Re => twiddle_zero, W_2l_Im => twiddle_zero,
W_3l_Re => twiddle_zero, W_3l_Im => twiddle_zero );
radix13 : radix_new1

port map ( x_Re =>sig_vector_Re12, xN4_Re => sig_vector_Re13,
xN2_Re => sig_vector_Re14, x3N4_Re=> sig_vector_Re15,
x_Im => sig_vector_Im12, xN4_Im =>sig_vector_Im13,
xN2_Im => sig_vector_Im14, x3N4_Im => sig_vector_Im15,
y_Re => X_out_Re3, g_Re => X_out_Re11,
z_Re => X_out_Re7, h_Re => X_out_Re15,
y_Im => X_out_Im3, g_Im => X_out_Im11,
z_Im => X_out_Im7, h_Im => X_out_Im15,
clk => clk,reset => reset, column => column1,
W_l_Re => twiddle_zero , W_l_Im =>twiddle_zero ,
W_2l_Re => twiddle_zero, W_2l_Im => twiddle_zero,
W_3l_Re => twiddle_zero, W_3l_Im => twiddle_zero );
out_R0 <=x_out_Re0;
out_R1 <=x_out_Re1;
out_R2 <=x_out_Re2;
out_R3 <=x_out_Re3;
out_R4 <=x_out_Re4;
out_R5 <=x_out_Re5;
out_R6 <=x_out_Re6;
out_R7 <=x_out_Re7;
out_R8 <=x_out_Re8;
out_R9 <=x_out_Re9;
outR10 <=x_out_Re10;
outR11 <=x_out_Re11;
outR12 <=x_out_Re12;
outR13 <=x_out_Re13;
outR14 <=x_out_Re14;
outR15 <=x_out_Re15;
out_I0 <=x_out_Im0;
out_I1 <=x_out_Im1;
out_I2 <=x_out_Im2;
out_I3 <=x_out_Im3;
out_I4 <=x_out_Im4;
out_I5 <=x_out_Im5;
out_I6 <=x_out_Im6;
out_I7 <=x_out_Im7;
out_I8 <=x_out_Im8;
out_I9 <=x_out_Im9;
outI10 <=x_out_Im10;
outI11 <=x_out_Im11;
outI12 <=x_out_Im12;
outI13 <=x_out_Im13;
outI14 <=x_out_Im14;
outI15 <=x_out_Im15;
end structural; ..............

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